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? semiconductor components industries, llc, 2014 august, 2014 ? rev. 10 1 publication order number: mc14066b/d mc14066b quad analog switch/quad multiplexer the mc14066b consists of four independent switches capable of controlling either digital or analog signals. this quad bilateral switch is useful in signal gating, chopper, modulator, demodulator and cmos logic implementation. the mc14066b is designed to be pin?for?pin compatible with the mc14016b, but has much lower on resistance. input voltage swings as large as the full supply voltage can be controlled via each independent control input. features ? triple diode protection on all control inputs ? supply voltage range = 3.0 vdc to 18 vdc ? linearized transfer characteristics ? low noise ? 12 nv/ cycle , f 1.0 khz typical ? pin?for?pin replacement for cd4016, cd4016, mc14016b ? for lower r on , use the hc4066 high?speed cmos device ? nlv prefix for automotive and other applications requiring unique site and control change requirements; aec?q100 qualified and ppap capable ? these devices are pb?free and are rohs compliant maximum ratings (voltages referenced to v ss ) symbol parameter value unit v dd dc supply voltage range ?0.5 to +18.0 v v in , v out input or output voltage range (dc or transient) ?0.5 to v dd + 0.5 v i in input current (dc or transient) per control pin 10 ma i sw switch through current 25 ma p d power dissipation, per package (note 1) 500 mw t a ambient temperature range ?55 to +125 c t stg storage temperature range ?65 to +150 c t l lead temperature (8?second soldering) 260 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. temperature derating: ?d/dw? packages: ?7.0 mw/ c from 65 c to 125 c this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high?impedance circuit. for proper operation, v in and v out should be constrained to the range v ss (v in or v out ) v dd . unused inputs must always be tied to an appropriate logic voltage level (e.g., either v ss or v dd ). unused outputs must be left open. http://onsemi.com marking diagrams soic?14 tssop?14 1 14 14066bg awlyww 14 066b alyw 1 14 a = assembly location wl, l = wafer lot yy, y = year ww, w = work week g or = pb?free package soeiaj?14 1 14 mc14066b alywg see detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. ordering information (note: microdot may be in either location) soic?14 d suffix case 751a tssop?14 dt suffix case 948g soeiaj?14 f suffix case 965 pin assignment 11 12 13 14 8 9 10 5 4 3 2 1 7 6 out 4 in 4 control 4 control 1 v dd in 3 out 3 in 2 out 2 out 1 in 1 v ss control 3 control 2
mc14066b http://onsemi.com 2 logic diagram and truth table (1/4 of device shown) block diagram in/out control out/in in 4 control 4 in 3 control 3 in 2 control 2 in 1 control 1 out 1 out 2 out 3 out 4 13 1 5 4 6 8 12 11 2 3 9 10 v dd = pin 14 v ss = pin 7 control switch 0=v ss off 1=v dd on logic diagram restrictions v ss v in v dd v ss v out v dd circuit schematic (1/4 of circuit shown) v dd v dd v dd v dd v dd v dd v dd v ss v ss v ss 300 cmos input
mc14066b http://onsemi.com 3 electrical characteristics characteristic symbo l v dd test conditions ?55 c 25 c 125 c uni t min max min typ (note 2) max min max supply requirements (voltages referenced to v ee ) power supply voltage range v dd ? 3.0 18 3.0 ? 18 3.0 18 v quiescent current per package i dd 5.0 10 15 control inputs: v in = v ss or v dd , switch i/o: v ss v i/o v dd , and v switch 500 mv (3) ? ? ? 0.25 0.5 1.0 ? ? ? 0.005 0.010 0.015 0.25 0.5 1.0 ? ? ? 7.5 15 30 a total supply current (dynamic plus quiescent, per package i d(av) 5.0 10 15 t a = 25 c only the channel component, (v in ? v out )/r on , is not included.) (0.07 a/khz) f + i dd typical (0.20 a/khz) f + i dd (0.36 a/khz) f + i dd a control inputs (voltages referenced to v ss ) low?level input voltage v il 5.0 10 15 r on = per spec, i off = per spec ? ? ? 1.5 3.0 4.0 ? ? ? 2.25 4.50 6.75 1.5 3.0 4.0 ? ? ? 1.5 3.0 4.0 v high?level input voltage v ih 5.0 10 15 r on = per spec, i off = per spec 3.5 7.0 11 ? ? ? 3.5 7.0 11 2.75 5.50 8.25 ? ? ? 3.5 7.0 11 ? ? ? v input leakage current i in 15 v in = 0 or v dd ? 0.1 ? 0.00001 0.1 ? 1.0 a input capacitance c in ? ? ? ? 5.0 7.5 ? ? pf switches in and out (voltages referenced to v ss ) recommended peak?to?peak voltage into or out of the switch v i/o ? channel on or off 0 v dd 0 ? v dd 0 v dd v p?p recommended static or dynamic voltage across the switch (note 3) (figure 1) v switch ? channel on 0 600 0 ? 600 0 300 mv output offset voltage v oo ? v in = 0 v, no load ? ? ? 10 ? ? ? v on resistance r on 5.0 10 15 v switch 500 mv (3) , v in = v il or v ih (control), and v in = 0 to v dd (switch) ? ? ? 800 400 220 ? ? ? 250 120 80 1050 500 280 ? ? ? 1200 520 300 on resistance between any two channels in the same package r on 5.0 10 15 ? ? ? 70 50 45 ? ? ? 25 10 10 70 50 45 ? ? ? 135 95 65 off?channel leakage current (figure 6) i off 15 v in = v il or v ih (control) channel to channel or any one channel ? 100 ? 0.05 100 ? 1000 na capacitance, switch i/o c i/o ? switch off ? ? ? 10 15 ? ? pf capacitance, feedthrough (switch off) c i/o ? ? ? ? ? 0.47 ? ? ? pf product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 2. data labeled ?typ? is not to be used for design purposes, but is intended as an indication of the ic?s potential performance. 3. for voltage drops across the switch ( v switch ) > 600 mv ( > 300 mv at high temperature), excessive v dd current may be drawn; i.e. the current out of the switch may contain both v dd and switch input components. the reliability of the device will be unaffected unless the maximum ratings are exceeded. (see first page of this data sheet.)
mc14066b http://onsemi.com 4 electrical characteristics (note 4) (c l = 50 pf, t a = 25 c unless otherwise noted.) characteristic symbol v dd vdc min typ (note 5) max unit propagation delay times v ss = 0 vdc input to output (r l = 10 k ) t plh , t phl = (0.17 ns/pf) c l + 15.5 ns t plh , t phl = (0.08 ns/pf) c l + 6.0 ns t plh , t phl = (0.06 ns/pf) c l + 4.0 ns t plh , t phl 5.0 10 15 ? ? ? 20 10 7.0 40 20 15 ns control to output (r l = 1 k ) (figure 2) output ?1? to high impedance t phz 5.0 10 15 ? ? ? 40 35 30 80 70 60 ns output ?0? to high impedance t plz 5.0 10 15 ? ? ? 40 35 30 80 70 60 ns high impedance to output ?1? t pzh 5.0 10 15 ? ? ? 60 20 15 120 40 30 ns high impedance to output ?0? t pzl 5.0 10 15 ? ? ? 60 20 15 120 40 30 ns second harmonic distortion v ss = ? 5 vdc (v in = 1.77 vdc, rms centered @ 0.0 vdc, r l = 10 k , f = 1.0 khz) ? 5.0 ? 0.1 ? % bandwidth (switch on) (figure 3) v ss = ? 5 vdc (r l = 1 k , 20 log (v out /v in ) = ? 3 db, c l = 50 pf, v in = 5 v p?p ) ? 5.0 ? 65 ? mhz feedthrough attenuation (switch off) v ss = ? 5 vdc (v in = 5 v p?p , r l = 1 k , f in = 1.0 mhz) (figure 3) ? 5.0 ? ? 50 ? db channel separation (figure 4) v ss = ? 5 vdc (v in = 5 v p?p , r l = 1 k , f in = 8.0 mhz) (switch a on, switch b off) ? 5.0 ? ? 50 ? db crosstalk, control input to signal output (figure 5) v ss = ? 5 vdc (r 1 = 1 k , r l = 10 k , control t tlh = t thl = 20 ns) ? 5.0 ? 300 ? mv p?p 4. the formulas given are for the typical characteristics only at 25 c. 5. data labelled ?typ? is not to be used for design purposes but is intended as an indication of the ic?s potential performance.
mc14066b http://onsemi.com 5 test circuits figure 1. v across switch figure 2. turn?on delay time test circuit and waveforms figure 3. bandwidth and feedthrough attenuation figure 4. channel separation figure 5. crosstalk, control to output figure 6. off channel leakage control section of ic source v load on switch v out v out v c v c v out v in r l c l 20 ns v dd v ss 90% 50% 10% t pzh t phz t pzl t plz 10% 90% 10% v x v out c l r l v dd v ss v c v in v dd - v ss 2 v dd - v ss 2 v in v dd v ss r l c l r l c l v in 1 k v out r l c l = 50 pf v c = -5.0 v to +5.0 v swing v c = v dd for bandwidth test v c = v ss for feedthrough test off channel under test v dd v ss v ss v dd a control section of ic 90% v in = v dd v x = v ss v in = v ss v x = v dd 10 k
mc14066b http://onsemi.com 6 figure 7. channel resistance (r on ) test circuit v dd v ss 10 k v dd keithley 160 digital multimeter 1 k range x-y plotter typical resistance characteristics figure 8. v dd = 7.5 v, v ss = ? 7.5 v figure 9. v dd = 5.0 v, v ss = ? 5.0 v r on , on resistance (ohms) 350 300 250 200 150 100 0 50 -8.0 -10 -6.0 -4.0 -2.0 0 0.2 4.0 6.0 8.0 10 v in , input voltage (volts) t a = 125 c 25 c -55 c r on , on resistance (ohms) 350 300 250 200 150 100 0 50 -8.0 -10 -6.0 -4.0 -2.0 0 0.2 4.0 6.0 8.0 10 v in , input voltage (volts) t a = 125 c 25 c -55 c figure 10. v dd = 2.5 v, v ss = ? 2.5 v r on , on resistance (ohms) 700 600 500 400 300 200 0 100 -8.0 -10 -6.0 -4.0 -2.0 0 0.2 4.0 6.0 8.0 10 v in , input voltage (volts) t a = 125 c 25 c -55 c figure 11. comparison at 25 c, v dd = ? v ss r on , on resistance (ohms) 350 300 250 200 150 100 0 50 -8.0 -10 -6.0 -4.0 -2.0 0 0.2 4.0 6.0 8.0 10 v in , input voltage (volts) t a = 25 c v dd = 2.5 v 5.0 v 7.5 v
mc14066b http://onsemi.com 7 applications information figure a illustrates use of the analog switch. the 0?to?5 v digital control signal is used to directly control a 5 v peak?to?peak analog signal. the digital control logic levels are determined by v dd and v ss . the v dd voltage is the logic high voltage, the v ss voltage is logic low. for the example, v dd = +5 v = logic high at the control inputs; v ss = gnd = 0 v = logic low. the maximum analog signal level is determined by v dd and v ss . the analog voltage must not swing higher than v dd or lower than v ss . the example shows a 5 v peak?to?peak signal which allows no margin at either peak. if voltage transients above v dd and/or below v ss are anticipated on the analog channels, external diodes (d x ) are recommended as shown in figure b. these diodes should be small signal types able to absorb the maximum anticipated current surges during clipping. the absolute maximum potential difference between v dd and v ss is 18 v. most parameters are specified up to 15 v which is the recommended maximum difference between v dd and v ss . figure a. application example +5 v v dd v ss 5 v p-p analog signal 0-to-5 v digital control signals switch in mc14066b switch out 5 v p-p analog signal +5.0 v + 2.5 v gnd +5 v external cmos digital circuitry figure b. external germanium or schottky clipping diodes v dd v dd v ss v ss d x d x d x d x switch in switch out
mc14066b http://onsemi.com 8 ordering information device package shipping ? mc14066bdg soic?14 (pb?free) 55 units / rail nlv14066bdg* soic?14 (pb?free) 55 units / rail MC14066BDR2G soic?14 (pb?free) 2500 / tape & reel nlv14066bdr2g* soic?14 (pb?free) 2500 / tape & reel mc14066bdtr2g tssop?14 (pb?free) 2500 / tape & reel nlv14066bdtr2g* tssop?14 (pb?free) 2500 / tape & reel mc14066bfelg soeiaj?14 (pb?free) 2000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. *nlv prefix for automotive and other applications requiring unique site and control change requirements; aec?q100 qualified and ppap capable.
mc14066b http://onsemi.com 9 package dimensions soic?14 nb case 751a?03 issue k notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b does not include dambar protrusion. allowable protrusion shall be 0.13 total in excess of at maximum material condition. 4. dimensions d and e do not include mold protrusions. 5. maximum mold protrusion 0.15 per side. h 14 8 7 1 m 0.25 b m c h x 45 seating plane a1 a m s a m 0.25 b s c b 13x b a e d e detail a l a3 detail a dim min max min max inches millimeters d 8.55 8.75 0.337 0.344 e 3.80 4.00 0.150 0.157 a 1.35 1.75 0.054 0.068 b 0.35 0.49 0.014 0.019 l 0.40 1.25 0.016 0.049 e 1.27 bsc 0.050 bsc a3 0.19 0.25 0.008 0.010 a1 0.10 0.25 0.004 0.010 m 0 7 0 7 h 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.019 6.50 14x 0.58 14x 1.18 1.27 dimensions: millimeters 1 pitch soldering footprint* *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d.
mc14066b http://onsemi.com 10 package dimensions tssop?14 case 948g issue b dim min max min max inches millimeters a 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c ??? 1.20 ??? 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.50 0.60 0.020 0.024 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane ?w?. s u 0.15 (0.006) t 2x l/2 s u m 0.10 (0.004) v s t l ?u? seating plane 0.10 (0.004) ?t? ??? ??? 0.25 (0.010) 8 14 7 1 pin 1 ident. h g a d c b s u 0.15 (0.006) t ?v? 14x ref k n n 7.06 14x 0.36 14x 1.26 0.65 dimensions: millimeters 1 pitch soldering footprint* *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d.
mc14066b http://onsemi.com 11 package dimensions soeiaj?14 case 965 issue b h e a 1 dim min max min max inches --- 2.05 --- 0.081 millimeters 0.05 0.20 0.002 0.008 0.35 0.50 0.014 0.020 0.10 0.20 0.004 0.008 9.90 10.50 0.390 0.413 5.10 5.45 0.201 0.215 1.27 bsc 0.050 bsc 7.40 8.20 0.291 0.323 0.50 0.85 0.020 0.033 1.10 1.50 0.043 0.059 0 0.70 0.90 0.028 0.035 --- 1.42 --- 0.056 a 1 h e q 1 l e 10 0 10 l e q 1 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions d and e do not include mold flash or protrusions and are measured at the parting line. mold flash or protrusions shall not exceed 0.15 (0.006) per side. 4. terminal numbers are shown for reference only. 5. the lead width dimension (b) does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the lead width dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. minimum space between protrusions and adjacent lead to be 0.46 ( 0.018). 0.13 (0.005) m 0.10 (0.004) d z e 1 14 8 7 e a b view p c l detail p m a b c d e e l m z on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemni fy and hold scillc and its officers, em ployees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 mc14066b/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative

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